Latches represent a large portion of the silicon area in logic semiconductor chips. This is especially true for CMOS gate arrays where latches require either devices of different sizes or a large number of identical devices: statistics indicate that 20 to 50 percent of the silicon area in CMOS gate arrays is used by latches, the average value being around 40 percent.
The Polarity Hold SRL (PHSRL) is one of the most frequently used, and therefore it has been chosen to illustrate the present application. FIG. 1A of the present application shows a known implementation in a Master Image environment when two outputs and one single ended data input are used. The PHSRL 10 of the D type master-slave flip-flop, is composed of two sections, known in the art as a "master" section and a "slave" section, referenced M1 and S1; respectively. For example, M1 is conventionally driven by a standard inverter Ill for the data input DO and a by pass transistor (transmission gate) T13 for the C clock. Two output buffers MB1 and SB1 are also provided for data outputs L11 and L12. FIG. 1B schematically details the functional structure of the master section M1 of PHSRL 10 of FIG. 1A. Each of the sections may also be viewed as an inverting latch cell. One general type of prior art inverting latch cell, (e.g. M1) typical of CMOS digital logic implementation, comprises a CMOS transmission gate T13 at the cell input supplying a pair of cross-coupled CMOS inverters I12 and I13. In the cross-coupled configuration, the output of one inverter is directly connected to the input of the other inverter, and the output of the other inverter is directly connected to the input of the one inverter. FIG. 1B shows clearly the two stage structure resulting from cross coupling the two inverters I12 and I13. Each stage is provided with a pair of voltage supply nodes, each connected to first and second supply voltages (Vdd and Ground). A standard CMOS inverter such as I12 includes a complementary pair of IGFETs T14 and T15. Thus, each inverting latch cell or section includes five IGFETs, for a total of ten IGFETs in the overall D-type master-slave flip-flop.
To form a D-type flip-flop master-slave, as represented in FIG. 1A, the two inverting latch cells are connected in
series, with the clock inputs C and C connected to the two transmission gates T13 and Tla respectively so that the transmission gates are alternately enabled. Typically, the transmission gate T13 of the first or "master" section is enabled when the clock input C is high, and the transmission gate of the second or "slave" section is enabled when the clock input C is high.
In general operation, with the clock C input high, input data DO is passed via the master section transmission gate T13 into the master section latch M1 comprising a pair of cross coupled inverters I12 and I13. When the clock input C goes low, the transmission gate T13 of the master section M1 is no longer enabled, isolating the data input DO from the flip-flop. At the same time, the slave section transmission Tl1a gate is enabled, coupling inverted data from the master section into the latch of the slave section, where the data appear at the output -L12. When the clock C goes low, the transmission gate Tla of the slave section is no longer enabled, isolating the slave section from the rest of the flip-flop, and the slave section accordingly retains the output logic voltage level until a subsequent low to high clock transition.
In any case, the integrated circuit typically includes a number of other elements supporting the flip-flop circuit. These other elements include, at least, voltage supply lines or nodes connected to a positive voltage VDD and the ground GND. Also, typical D-type master-slave flip-flops require complementary clock inputs (e.g. C and C) and an inverter will typically be included, common to a number of individual D-type master-slave flip-flops to provide said complementary clock inputs. Latch M1 has a data input (DO input), either one or a pair of complementary data outputs PL11 and ML11, and a clock input. In operation, a logic state is retained or latched at the output or outputs indefinitely as long as the clock level remains low (binary "0"). Data, in the form of a logic level, is transferred to the data output (PL11 output) upon a specified clock pulse edge or transition of the clock input from logic low to logic high. If provided, complementary data is available at the ML11 output. Dissymmetry between the inverters is necessary, otherwise the latch cell will never switch when a single ended data input is used.
This PHSRL 10 uses a minimum number of devices but requires different sizes of devices (transistors) to assure that this dissymmetry is obtained. For example device T14 (or T15) in series with Tla must have a lower impedance than T1e (or T1d), in order to avoid disturbing the state of the master when transferring the data into the slave when transistor T1a is switched on by clock C. T11 (or T12) in series with T13 must also have a lower impedance than T17 (or T16) to insure that the input DO will force the state into the latch when T13 is switched on by the clock C.
In other words, during the latch switching with the clock active (high level), two parasitic currents have to be considered to insure a good functionality:
______________________________________ For D0 = 1 path from VDD to GND thru devices T16-T13-T12 For D0 = 0 path from VDD to GND thru devices T11-T13-T17 ______________________________________
These parasitic currents may be reduced by decreasing the size of devices T16 and T17 used in inverter I13, by reducing the W/L ratio.
In a Master Image environment, this differentiation is obtained by personalizing the silicon for each circuit to provide devices of different electrical characteristics. In a Masterslice environment such as described here, this is obtained by creating different device sizes in the silicon substrate. This latter technique makes the physical drawing of the cell more sophisticated and generally less efficient for the rest of the logic books because the granularity of the cell becomes larger.
Unlike the master Image approach, the gate array philosophy which appears to be the most promising technology available today is different: only one N and one P device types are used in order to keep the cell granularity small. This has led to high performance symmetrical latches. A fast CMOS PHSRL is shown in the IBM Technical Disclosure Bulletin, vol. 27, No. 7A, December 1984, pp 3894-3896 in an article entitled "Fast shift register latch in CMOS technology" authored by R. Hornung et al. FIG. 2A shows a simplified version of the gate array implementation of this PHSRL, when extra circuits due to LSSD technique (Level Sensitive Scan Design) have been removed. PHSRL 20 performs the same function as the version of FIG. 1A but it has been redesigned for sake of simplicity and comparison. To switch the "master" latch cell M2 from one state to the opposite state needs a symmetrical command by DO and DO simultaneously on the two sides of the latch cell through transmission gates T23 and T28. This is made necessary here because in gate arrays, all the devices (transistors) have the same size. This particular implementation of a latch cell uses 8 transistors, compared with the 5 transistor latch cell in the Master Image approach. It is 40% faster and dissipates 1.8 times more power than the version shown in FIG. 1A at same, clock frequency. It has, therefore, very attractive performance. Unfortunately due to its symmetrical implementation, the density is lower compared with the latch shown in FIG. 1 where different device sizes permit a single ended data input with a lower transistor count.
FIG. 2B schematically details the functional structure of the master section M2 of PHSRL 20 of FIG. 2A, and more particularly, points out that with such an implementation the output of one inverter I22 is directly coupled to the input of the other inverter I23, and the output of the other inverter I23 is connected to the input of the one inverter I22 The data DO is applied on the input of inverter I23 through transmission gate T23 and its complementary value DO is applied to the input of inverter I22 through a standard transmission T28 gate and an inverter comprised of a pair of complementary IGFETS: T29 and T2a.
It is to be noted that in both versions of FIG. 1A or FIG. 1B, the master and slave sections are identical.